The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Aug. 08, 2018
Applicant:

Tdk Corporation, Tokyo, JP;

Inventors:

Yuji Kakinuma, Tokyo, JP;

Atsushi Tsumita, Tokyo, JP;

Assignee:

TDK CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 43/02 (2006.01); H01L 27/22 (2006.01); G11C 11/16 (2006.01); H01F 10/32 (2006.01); G11C 11/18 (2006.01); H01L 43/06 (2006.01); H01L 43/08 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 11/18 (2013.01); H01F 10/329 (2013.01); H01L 27/228 (2013.01); H01L 43/06 (2013.01); H01L 43/08 (2013.01);
Abstract

Provided is a magnetic memory including: a first bit line, a second bit line, and a third bit line; a word line; a first magnetoresistance effect element; a first transistor; a second magnetoresistance effect element; and a second transistor, wherein free layers of the first and second magnetoresistance effect elements and the second bit line are connected, a fixed layer of the first magnetoresistance effect element and a source terminal of the first transistor are connected, a drain terminal of the first transistor and the first bit line are connected, a fixed layer of the second magnetoresistance effect element and a drain terminal of the second transistor are connected, a source terminal of the second transistor and the third bit line are connected, and the word line is connected to each of a gate terminal of the first transistor and a gate terminal of the second transistor.


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