The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Jun. 01, 2018
Applicant:

Artilux, Inc., Menlo Park, CA (US);

Inventors:

Szu-Lin Cheng, Zhubei, TW;

Han-Din Liu, Zhubei, TW;

Shu-Lu Chen, Zhubei, TW;

Yun-Chung Na, Hsinchu, TW;

Hui-Wen Chen, Hsinchu, TW;

Assignee:

Artilux, Inc., Menlo Park, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/18 (2006.01); H01L 27/146 (2006.01); H01L 31/0232 (2014.01); H01L 31/02 (2006.01); H01L 31/0216 (2014.01); H01L 31/107 (2006.01); H01L 31/054 (2014.01); H01L 31/105 (2006.01); H01L 31/028 (2006.01);
U.S. Cl.
CPC ...
H01L 31/1812 (2013.01); H01L 27/1469 (2013.01); H01L 27/14629 (2013.01); H01L 27/14634 (2013.01); H01L 31/02005 (2013.01); H01L 31/028 (2013.01); H01L 31/02161 (2013.01); H01L 31/02327 (2013.01); H01L 31/0549 (2014.12); H01L 31/105 (2013.01); H01L 31/107 (2013.01); H01L 31/1892 (2013.01); Y02E 10/52 (2013.01); Y02E 10/547 (2013.01);
Abstract

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.


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