The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Mar. 01, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Go Shikata, Yokohama Kanagawa, JP;

Yasuhiro Shimura, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); G11C 7/06 (2006.01); G11C 8/08 (2006.01); G06F 11/10 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); G06F 11/1044 (2013.01); G11C 7/06 (2013.01); G11C 8/08 (2013.01); G11C 16/08 (2013.01); G11C 16/0483 (2013.01);
Abstract

A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.


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