The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Feb. 05, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Roger A. Quon, Rhinebeck, NY (US);

Michael Rizzolo, Albany, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/768 (2006.01); C23C 16/56 (2006.01); C23C 14/58 (2006.01); C23C 14/04 (2006.01); C23C 14/56 (2006.01); C23C 16/04 (2006.01); C23C 16/06 (2006.01); C23C 16/34 (2006.01); C23C 16/455 (2006.01); C23C 16/50 (2006.01); C23C 18/52 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76882 (2013.01); C23C 14/046 (2013.01); C23C 14/568 (2013.01); C23C 14/5806 (2013.01); C23C 14/5873 (2013.01); C23C 16/045 (2013.01); C23C 16/06 (2013.01); C23C 16/34 (2013.01); C23C 16/45544 (2013.01); C23C 16/50 (2013.01); C23C 16/56 (2013.01); C23C 18/52 (2013.01); H01L 21/67 (2013.01);
Abstract

Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate microstructures of metallic interconnect structures. For example, an apparatus includes a single platform semiconductor processing chamber having first and second sub-chambers. The first sub-chamber is configured to receive a semiconductor substrate comprising a metallization layer formed on a dielectric layer, wherein a portion of the metallization layer is disposed within an opening etched in the dielectric layer, and to form a stress control layer on the metallization layer. The second sub-chamber comprises a programmable hot plate which is configured to perform a thermal anneal process to modulate a microstructure of the metallization layer while the stress control layer is disposed on the metallization layer, and without an air break between the process modules of forming the stress control layer and performing the thermal anneal process.


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