The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Jul. 20, 2018
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Jung Hwan Ji, Hwaseong-si, KR;

Sang Ho Lee, Cheongju-si, KR;

Ho Don Jung, Seoul, KR;

Jun Hyun Chun, Yongin-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 16/08 (2006.01); G11C 8/10 (2006.01); G11C 11/408 (2006.01); G11C 7/18 (2006.01); G11C 8/12 (2006.01); G11C 5/02 (2006.01); G11C 11/4097 (2006.01); G11C 7/08 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 5/025 (2013.01); G11C 7/18 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 11/4087 (2013.01); G11C 11/4097 (2013.01); G11C 7/08 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G11C 2207/005 (2013.01);
Abstract

A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.


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