The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Jul. 19, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Young-Hwa Kim, Seongnam-si, KR;

Tae-Young Oh, Seoul, KR;

Jin-Hun Jang, Uiwang-si, KR;

Seok-Jin Cho, Taipei, TW;

Kyung-Soo Ha, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 5/147 (2013.01);
Abstract

A memory device has a plurality of power rails, including: a first power rail for transmitting a high power voltage, a second power rail for transmitting a low power voltage, a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied. When power gating is applied, supply of the power voltage to the fourth power rail is blocked.


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