Apparatus and method for efficient utilisation of an address translation cache

Abstract

An apparatus and method are provided for efficient utilisation of an address translation cache. The apparatus has an address translation cache with a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each entry identifies whether the address translation data stored therein is coalesced or non-coalesced address translation data, and also identifies a page size for a page within the memory system that is associated with that address translation data. Control circuitry is responsive to a virtual address, to perform a lookup operation within the address translation cache to produce, for each page size supported by the address translation cache, a hit indication to indicate whether a hit has been detected for an entry storing address translation data of the associated page size. The control circuitry is further arranged to determine, from at least each hit indication for a page size that is able to be associated with coalesced address translation data, a coalesced multi-hit indication which is set when a hit is detected for both an entry containing coalesced address translation data and for an entry containing non-coalesced address translation data. The control circuitry is then arranged, when the lookup operation has completed, to determine whether multiple hits have been detected, and in that instance to reference the coalesced multi-hit indication to determine whether multiple hits have resulted from both coalesced address translation data and non-coalesced address translation data in the address translation cache. This provides an efficient and precise mechanism for distinguishing between multiple hits caused by hardware coalescing and multiple hits caused by software induced issues.