The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Nov. 02, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Masahiro Ishiyama, Kawasaki Kanagawa, JP;

Shigehiro Asano, Yokosuka Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/064 (2013.01); G06F 3/0611 (2013.01); G06F 3/0688 (2013.01); G06F 11/108 (2013.01); G06F 1/3203 (2013.01);
Abstract

A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller. The controller manages a plurality of logical areas for storing data portions received from the host and parities calculated from the data portions, the logical areas including first and second logical areas for storing first and second parity groups, respectively. Each first parity group includes k data portions received from the host and m parities calculated therefrom. Each second parity group includes k' data portions received from the host and m′ parities calculated therefrom. Also, the controller maps each logical area to storage locations in the non-volatile memory dies such that the data portions and the parities of any one parity group are each stored in a different physical block in a set of physical blocks selected from different non-volatile memory dies.


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