The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10528418 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 07, 2020

Filed:

Oct. 30, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lakshminarayana B. Arimilli, Austin, TX (US);

Richard L. Arndt, Austin, TX (US);

Bartholomew Blaner, Shelburne, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 12/126 (2016.01); G06F 9/455 (2018.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 11/0793 (2013.01); G06F 9/45558 (2013.01); G06F 11/073 (2013.01); G06F 11/079 (2013.01); G06F 11/0712 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 12/1009 (2013.01); G06F 12/126 (2013.01); G06F 13/1673 (2013.01); G06F 13/4022 (2013.01); G06F 2212/65 (2013.01);
Abstract

Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation. The switchboard forwards the operation with the repaired memory address translation from the second buffer to a first buffer and the hardware accelerator executes the operation with the repaired address.


Find Patent Forward Citations

Arimilli, Lakshminarayana. (2020). Hardware accelerator address translation fault resolution (U.S. Patent No. 10528418). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10528418

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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