The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Jan. 04, 2019
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Masanobu Ikeda, Tokyo, JP;

Koji Ishizaki, Tokyo, JP;

Hayato Kurasawa, Tokyo, JP;

Yoshihiro Watanabe, Tokyo, JP;

Toshimasa Ishigaki, Tokyo, JP;

Daisuke Sonoda, Tokyo, JP;

Tatsuya Ide, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/044 (2006.01); G02F 1/1333 (2006.01); G06F 3/041 (2006.01); G02F 1/1362 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G06F 3/044 (2013.01); G02F 1/13338 (2013.01); G02F 1/136204 (2013.01); G06F 3/0412 (2013.01); G02F 2001/134372 (2013.01);
Abstract

To reduce disturbances in display of images due to static electricity without deteriorating optical properties in a display. The display includes a conductive pattern provided on the upper surface of the substrate, a protection layer provided on the upper surface of the substrate to cover the conductive pattern, and a conductive layer provided on the protection layer. The sheet resistance of the conductive pattern is not more than 8 Ω/square. A ratio of the total sum of areas of portions of the plurality of sub-pixels that overlap the conductive pattern in a plan view to the total sum of the areas of the plurality of sub-pixels is 1 to 22%. A sheet resistance of the conductive layer is higher than the sheet resistance of the conductive pattern.


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