The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Nov. 21, 2017
Applicant:

The Boeing Company, Chicago, IL (US);

Inventors:

Wing C. Lee, San Marino, CA (US);

Sean M. Ramey, Mill Creek, WA (US);

Ronald James Koontz, Mesa, AZ (US);

Dick P. Wong, Monterey Park, CA (US);

Jackson Chia, San Gabriel, CA (US);

Anthony S. Fornabaio, Scottsdale, AZ (US);

Murali Rangarajan, Chesterfield, MO (US);

Clarke Edgar Moore, Huntsville, AL (US);

David Clyde Sharp, St. Louis, MO (US);

Arnold W. Nordsieck, Bellevue, WA (US);

Paul Eugene Denzel, Bothell, WA (US);

Assignee:

The Boeing Company, Chicago, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 13/42 (2006.01); H04L 5/00 (2006.01); H04L 7/00 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 1/12 (2013.01);
Abstract

A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.


Find Patent Forward Citations

Loading…