The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Feb. 27, 2015
Applicant:

Ams Sensors Uk Limited, Cambridge, GB;

Inventors:

Florin Udrea, Cambridge, GB;

Syed Zeeshan Ali, Cambridge, GB;

Julian Gardner, Cambridge, GB;

Assignee:

AMS SENSORS UK LIMITED, Cambridgeshire, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/00 (2006.01); G01N 27/04 (2006.01); G01N 27/14 (2006.01); H05B 3/26 (2006.01); H05B 3/14 (2006.01); G01N 33/00 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
G01N 27/04 (2013.01); G01N 27/14 (2013.01); G01N 33/0027 (2013.01); H05B 3/143 (2013.01); H05B 3/26 (2013.01); H05B 3/265 (2013.01); H01L 21/8238 (2013.01); H05B 2203/013 (2013.01); H05B 2203/017 (2013.01);
Abstract

It is disclosed herein a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device is made using partly CMOS or CMOS based processing steps, and it includes a semiconductor substrate, a dielectric region over the semiconductor substrate, a heater within the dielectric region and a patterned layer of noble metal above the dielectric region. The method includes the deposition of a photoresist material over the dielectric region, and patterning the photo-resist material to form a patterned region over the dielectric region. The steps of depositing the photo-resist material and patterning the photo-resist material may be performed in sequence using similar photolithography and etching steps to those used in a CMOS process. The resulting semiconductor device is then subjected to further processing steps which ensure that a dielectric membrane and a metal structure within the membrane are formed in the patterned region over the dielectric region.


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