The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Dec. 10, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yu Zhang, Cary, NC (US);

Douglas Bruce White, Clayton, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 9/00 (2006.01); H05K 1/11 (2006.01); H05K 1/09 (2006.01); H05K 3/46 (2006.01); H05K 3/40 (2006.01); H05K 1/05 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0218 (2013.01); H05K 1/0234 (2013.01); H05K 1/0298 (2013.01); H05K 1/05 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 3/4038 (2013.01); H05K 3/46 (2013.01); H05K 9/0075 (2013.01); H05K 1/0251 (2013.01); H05K 1/116 (2013.01); H05K 2201/09663 (2013.01); H05K 2201/10022 (2013.01);
Abstract

Disclosed is a printed circuit board (PCB) including a set of stacked metallization layers separated by a set of stacked electrical-insulating layers, respectively, wherein the set of stacked metallization layers includes top metallization layer, bottom metallization layer, and intermediate metallization layer; a via electrically coupled to the top metallization layer, the intermediate metallization layer, and the bottom metallization layer, wherein the top metallization layer, a portion of the via between the top metallization layer and the intermediate metallization layer, and the intermediate metallization layer are configured to route a data signal between a signal-in and a signal-out; and an electromagnetic absorbing material configured to reduce an intensity of a reflected signal resulting from the data signal propagating downward along a stub of the via and reflecting off the bottom metallization layer. The electromagnetic absorbing material may be attached to a bottom of the PCB and/or coaxially attached to the stub.


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