The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

May. 26, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Madhukar Vallabhaneni, Bangalore, IN;

Girish Koppassery, Bangalore, IN;

Xinhua Chen, San Diego, CA (US);

Jingcheng Zhuang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 3/28 (2006.01); H04L 25/08 (2006.01); H05K 1/02 (2006.01); H01R 9/03 (2006.01); H01R 9/11 (2006.01); H01R 11/05 (2006.01); H01R 12/70 (2011.01); H01R 12/77 (2011.01); H01R 12/00 (2006.01); H04L 25/00 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H04B 3/28 (2013.01); H01R 9/034 (2013.01); H01R 9/11 (2013.01); H01R 11/05 (2013.01); H01R 12/00 (2013.01); H01R 12/7076 (2013.01); H01R 12/775 (2013.01); H04L 25/00 (2013.01); H04L 25/0274 (2013.01); H04L 25/085 (2013.01); H05K 1/0233 (2013.01);
Abstract

An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.


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