The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Sep. 27, 2018
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Hongyuan Zhang, Fremont, CA (US);

Sergey Timofeev, Mountain View, CA (US);

Lance Nagamine, Fremont, CA (US);

Tsunglun Yu, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/00 (2006.01); H04B 7/0413 (2017.01); H04B 7/0404 (2017.01); H04W 88/06 (2009.01);
U.S. Cl.
CPC ...
H04B 1/005 (2013.01); H04B 7/0404 (2013.01); H04B 7/0413 (2013.01); H04W 88/06 (2013.01);
Abstract

The present disclosure describes apparatuses and methods for a configurable wireless communication chip. In some aspects, a wireless communication chip includes multiple radio paths and is capable of operating in a first communication mode that supports communication in non-contiguous segments of bandwidth and a second communication mode that does not support communication in non-contiguous segments of bandwidth. Based on a hardware configuration external to the wireless communication chip, the radio paths can be configured to operate in the first communication mode or the second communication mode. In some cases, the hardware configuration external to the wireless communication chip includes fewer antennas or amplifier paths than radio paths of the chip, such as due to cost or form-factor considerations. In such cases, the wireless communication chip can operate in the second communication mode to implement advanced communication techniques with reduced hardware, enabling flexibility to design lower cost or smaller devices.


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