Phase locked loop and control method therefor

Abstract

The present technology relates to a phase locked loop and a control method therefor, which are capable of achieving low power consumption and good phase noise while suppressing the growth of circuit area. The phase locked loop includes: a digitally controlled oscillation unit that controls an oscillation frequency by a control signal in a digital format; a multiphase clock generation unit that generates clock signals with multiple phases synchronized with the digitally controlled oscillation unit; a clock selection unit that selects a selected clock signal out of the clock signals with multiple phases; a time-to-digital conversion unit that detects a time difference between the selected clock signal and a reference clock signal; a counter unit driven by any one clock signal out of the clock signals with multiple phases; a reference phase generation unit that generates a reference phase; a phase comparison unit that compares feedback phase information obtained from an output value of the counter unit and an output value of the time-to-digital conversion unit with the reference phase; and a digital loop filter unit that smooths output of the phase comparison unit and generates the control signal for the digitally controlled oscillation unit.