The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

May. 23, 2018
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Rajan Vijayaraghavan, Chandler, AZ (US);

Ajay Kumar, Phoenix, AZ (US);

Kiran Karnik, Chandler, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/36 (2006.01); H03B 5/06 (2006.01); H03L 1/02 (2006.01);
U.S. Cl.
CPC ...
H03B 5/364 (2013.01); H03B 5/06 (2013.01); H03L 1/028 (2013.01); H03B 2200/0012 (2013.01); H03B 2200/0094 (2013.01);
Abstract

Low voltage crystal oscillator having native NMOS transistors used for coupling/decoupling to/from GPIO. The native NMOS transistors function properly at a low supply voltage when on (low resistance) and a high supply voltage when off (high resistance). Oscillator Gm driver bias resistors are repurposed to degenerate the native NMOS transistors when they are off, thereby reducing the leakage current thereof (oscillator circuit decoupled from GPIO nodes). This ensures compliance with the CMOS IIH leakage current specification during an external clock (EC) mode at a high supply voltage.


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