The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Aug. 30, 2018
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Yusuke Kobayashi, Tsukuba, JP;

Manabu Takei, Tsukuba, JP;

Shinsuke Harada, Tsukuba, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 27/06 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7806 (2013.01); H01L 27/0629 (2013.01); H01L 29/0615 (2013.01); H01L 29/0696 (2013.01); H01L 29/1045 (2013.01); H01L 29/7813 (2013.01); H01L 29/1608 (2013.01);
Abstract

Plural trenches are provided in a semiconductor substrate. First p-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p-type regions disposed in a MOS cell region C' that is substantially half of a region between the adjacent second trenches is in a range of about 2 μm to 8 μm.


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