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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10522672 B1

PDFFull Text
Date of Patent:
Dec. 31, 2019

Filed:

Aug. 07, 2018

Semiconductor device

Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventor:

Naoki Kumagai, Nagano, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:

Chen Yoshimura LLP

Primary Examiner:

Thinh T Nguyen

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/085 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/8258 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 29/167 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7806 (2013.01); H01L 21/02529 (2013.01); H01L 21/0465 (2013.01); H01L 21/8258 (2013.01); H01L 27/085 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/4236 (2013.01); H01L 29/4916 (2013.01); H01L 29/66734 (2013.01); H01L 29/7811 (2013.01); H01L 29/7813 (2013.01); H01L 29/063 (2013.01); H01L 29/0619 (2013.01); H01L 29/1608 (2013.01); H01L 29/402 (2013.01);
Abstract

A semiconductor substrate made of silicon carbide is provided with first and second cells having a MOS gate structure. The first cell is a normal MOSFET cell. In the second cell, a gate electrode is directly connected to a source electrode and has a potential fixed to a potential of the source electrode. A thickness of a gate insulating film of the second cell is set to be less than a thickness of a gate insulating film of a first cell so that the surface potential of a p-type channel region of the second cell becomes lower than the surface potential of a p-type channel region of the first cell during a negative bias to the gate electrode of the first cell.

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