The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Apr. 26, 2018
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Takeshi Tawara, Tsukuba, JP;

Hidekazu Tsuchida, Yokosuka, JP;

Koichi Murata, Yokosuka, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/36 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7395 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02433 (2013.01); H01L 21/02447 (2013.01); H01L 21/02529 (2013.01); H01L 21/02579 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/36 (2013.01); H01L 29/66068 (2013.01);
Abstract

The SiC-IGBT includes a p-type collector layer, an n-type voltage-blocking-layer provided on the collector layer, p-type base regions provided on the n-type voltage-blocking-layer, n-type emitter regions provided in an upper portion of the p-type base region, a gate insulating film provided in an upper portion of the voltage-blocking-layer, and a gate electrode provided on the gate insulating film. The p-type buffer layer has thickness of five micrometers or more and 20 micrometers or less and is doped with Al at impurity concentration of 5×10cmor more and 5×10cmor less and doped with B at impurity concentration of 2×10cmor more and less than 5×10cm.


Find Patent Forward Citations

Loading…