The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2019
Filed:
Nov. 28, 2017
V-grooved vertical channel-type 3d semiconductor memory device and method for manufacturing the same
Applicant:
Imec Vzw, Leuven, BE;
Inventor:
Jan Van Houdt, Bekkevoort, BE;
Assignee:
IMEC vzw, Leuven, BE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/11597 (2017.01); H01L 27/11556 (2017.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 29/1037 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 27/11597 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/08 (2013.01); H01L 45/1226 (2013.01);
Abstract
A method of fabricating a vertical channel 3D semiconductor memory device is disclosed. In one aspect, the method comprises providing a stack of alternating layers of conductive material and dielectric material on a major surface of substrate, providing in the stack at least one trench, having sloped sidewalls sloping towards the major surface, extending at least below the lowest layer of conductive material, forming, in order, a programmable material, a channel liner, and a filler material on the sidewalls of the trench. Thereby, the method forms a memory string, and an electrode to the channel liner at opposite ends of the memory string.