The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Dec. 27, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Daigo Ichinose, Nagoya, JP;

Shigehiro Yamakita, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/11582 (2017.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/76805 (2013.01); H01L 21/76877 (2013.01); H01L 23/535 (2013.01); H01L 27/11582 (2013.01); H01L 28/20 (2013.01);
Abstract

A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.


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