The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Mar. 15, 2019
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Yuta Endo, Kanagawa, JP;

Hideomi Suzawa, Kanagawa, JP;

Sachiaki Tezuka, Kanagawa, JP;

Tetsuhiro Tanaka, Tokyo, JP;

Toshiya Endo, Kanagawa, JP;

Mitsuhiro Ichijo, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/8258 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76826 (2013.01); H01L 21/02321 (2013.01); H01L 21/76802 (2013.01); H01L 21/8258 (2013.01); H01L 21/823418 (2013.01); H01L 21/823462 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01); H01L 29/78651 (2013.01); H01L 29/78696 (2013.01);
Abstract

A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.


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