The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Sep. 04, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Hiromi Noro, Kawasaki, JP;

Tetsuya Fujita, Kawasaki, JP;

Keiji Maruyama, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/32 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G11C 7/06 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/222 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes, a memory cell array, a first clock signal line, a second clock signal line to which first and second input/output buffer circuits are coupled in the order from one end toward the other end, a first buffer coupled to the one end of the second clock signal line, and a second buffer coupled to the other end of the second clock signal line. When a write operation is performed, a clock signal is input to the first and second input/output buffer circuits through the first buffer, and when a read operation is performed, a clock signal is input to the first and second input/output buffer circuits through the second buffer.


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