The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Mar. 25, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Shigetsugu Yamanaka, Sakai, JP;

Noboru Noguchi, Sakai, JP;

Masanori Ohara, Sakai, JP;

Noritaka Kishi, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/3291 (2016.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3291 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0626 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01);
Abstract

A display device that is configured to include two independent shift registers and is capable of performing a monitoring process without causing the degradation of display quality or the occurrence of abnormal operation is implemented. In a display device including: a writing control shift register composed of a plurality of first unit circuits () each including a first boost circuit () and a first output node reset circuit (); and a monitoring control shift register composed of a plurality of second unit circuits () each including a second boost circuit () and a second output node reset circuit (), current drive capability of the first boost circuit () is higher than current drive capability of the second boost circuit (), and current drive capability of the second output node reset circuit () is higher than current drive capability of the first output node reset circuit ().


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