The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2019
Filed:
Jul. 01, 2019
Mythic, Inc., Austin, TX (US);
David Fick, Austin, TX (US);
Malav Parikh, Austin, TX (US);
Paul Toth, Austin, TX (US);
Adam Caughron, Austin, TX (US);
Vimal Reddy, Austin, TX (US);
Erik Schlanger, Austin, TX (US);
Sergio Schuler, Austin, TX (US);
Zainab Nasreen Zaidi, Austin, TX (US);
Alex Dang-Tran, Austin, TX (US);
Raul Garibay, Austin, TX (US);
Bryant Sorensen, Austin, TX (US);
Mythic, Inc., Austin, TX (US);
Abstract
Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.