The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Mar. 15, 2018
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventors:

Sumanranjan Mitra, Mumbai, IN;

Ajit Patil, Bangalore, IN;

Sivaprakash Rajaram, Madurai, IN;

Assignee:

Seagate Technology LLC, Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 13/42 (2006.01); G06F 11/30 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0664 (2013.01); G06F 3/0683 (2013.01); G06F 11/3034 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An apparatus may include a baseboard management controller (BMC) configured to monitor one or more statuses of a storage array enclosure of the BMC. The BMC may further communicate with a host device of a PCIe network topology via a PCIe port of the BMC including performing a direct memory access (DMA) write to store status information of the enclosure to a memory of the host device via the PCIe network topology and performing a DMA read to retrieve control information from the memory of the host device via the PCIe network topology. In addition, the BMC may control one or more devices of the storage array enclosure based on the retrieved control information.


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