The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Jan. 18, 2016
Applicant:

Palo Alto Research Center Incorporated, Palo Alto, CA (US);

Inventors:

Sourobh Raychaudhuri, Mountain View, CA (US);

Jeng Ping Lu, Fremont, CA (US);

David K. Biegelsen, Portola Valley, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81C 99/00 (2010.01); H01L 21/683 (2006.01); H02N 13/00 (2006.01);
U.S. Cl.
CPC ...
B81C 99/002 (2013.01); H01L 21/6833 (2013.01); H02N 13/00 (2013.01);
Abstract

An intermediate transfer surface includes a substrate, a two-dimensional array of electrodes, a dielectric spacer layer on the two-dimensional array of electrodes, and a voltage controller electrically connected to the array of electrodes. A method of manufacturing an intermediate transfer surface, depositing an array of etch stops on a conductive surface, etching the conductive surface to form mesas of the conductive surface separated by gaps, and coating the mesas with a dielectric coating. A microassembly system includes an assembly surface having a first two dimensional array of potential wells on a first surface, a first voltage source electrically connected to the first array of potential wells, an intermediate transfer surface having a second two dimensional array of potential wells on a second surface arranged to face the first surface, and a second voltage source electrically connected to the second array of potential wells.


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