The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2019
Filed:
Jan. 12, 2018
Applicant:
Longitude Semiconductor S.a.r.l., Luxembourg, LU;
Inventor:
Atsushi Tomohiro, Tokyo, JP;
Assignee:
LONGITUDE LICENSING LIMITED, Dublin, IE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/10 (2006.01); H05K 7/12 (2006.01); H05K 1/18 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 23/498 (2013.01); H01L 23/49827 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H05K 1/0203 (2013.01); H05K 1/111 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/181 (2013.01); H05K 2201/10159 (2013.01);
Abstract
One semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing body. The wiring substrate includes an insulating base material, a first conductive pattern formed on one surface of the insulating base material, and a second conductive pattern formed on one surface of the insulating base material, connected to the first conductive pattern and having an end face exposed to the side. The semiconductor chip is mounted on the wiring substrate so as to overlap with the first conductive pattern. The sealing body is formed on the wiring substrate so as to cover the semiconductor chip.