The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Aug. 31, 2017
Applicants:

Joongshik Shin, Yongin-si, KR;

Jihoon Park, Hwaseong-si, KR;

Yong-hoon Son, Yongin-si, KR;

Jongho Woo, Hwaseong-si, KR;

Euntaek Jung, Seongnam-si, KR;

Junho Cha, Seongnam-si, KR;

Inventors:

JoongShik Shin, Yongin-si, KR;

Jihoon Park, Hwaseong-si, KR;

Yong-Hoon Son, Yongin-si, KR;

Jongho Woo, Hwaseong-si, KR;

Euntaek Jung, Seongnam-si, KR;

Junho Cha, Seongnam-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/308 (2013.01); H01L 27/11565 (2013.01);
Abstract

A three-dimensional semiconductor device includes a substrate including a cell array region and a contact region, a stack structure including gate electrodes sequentially stacked on the substrate, vertical structures penetrating the stack structure, and cell contact plugs connected to end portions of the gate electrodes in the contact region. Upper surfaces of the end portions of the gate electrodes have an acute angle with respect to an upper surface of the substrate in the cell array region.


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