The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Dec. 11, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Ankit Kumar, Ranchi, IN;

Manoj Kumar, Dhanbad, IN;

Chia-Hao Lee, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11517 (2017.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11517 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.


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