The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

May. 14, 2018
Applicant:

Tdk Corporation, Tokyo, JP;

Inventors:

Kazutoshi Tsuyutani, Tokyo, JP;

Masashi Katsumata, Tokyo, JP;

Assignee:

TDK CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 24/96 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82005 (2013.01); H01L 2224/9222 (2013.01); H01L 2224/96 (2013.01);
Abstract

Disclosed herein is a circuit board that includes a first insulating layer having an upper surface; a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer such that the upper surface of the first wiring layer is substantially coplanar with the upper surface of the first insulating layer; a semiconductor IC mounted on the upper surface of the first wiring layer with a die attach material interposed therebetween; and a second insulating layer stacked on the upper surface of the first wiring layer so as to embed the semiconductor IC, wherein a bottom surface of the die attach material is in contact with both of the upper surface of the first insulating layer and the upper surface of the first wiring layer.


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