The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

May. 30, 2017
Applicant:

Sansha Electric Manufacturing Co., Ltd., Osaka, JP;

Inventors:

Kazunori Inami, Tsuyama, JP;

Takahiro Maruyama, Tsuyama, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/373 (2006.01); H01L 23/13 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 23/3735 (2013.01); H01L 23/49822 (2013.01);
Abstract

The present invention provides a laminated member that prevents contact of a semiconductor chip and an external leading terminal etc. without increasing the number of components. The laminated member is a laminated member having a three-layer structure, comprising: an upper highly thermally conductive layer; a lower highly thermally conductive layer; and an intermediate layer having a low thermal expansion coefficient, wherein the above-described laminated member is larger than the above-described semiconductor chip in a plan view, and wherein a height position of the above-described first peripheral edge area is located at a certain distance below a height position of the above-described first bonding area, and a height position of the second peripheral edge area of the above-described second bonding area is located at a certain distance above a height position of the above-described second bonding area.


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