The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Oct. 18, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Weihan Wang, Tokyo, JP;

Takahiro Shimizu, Yokohama Kanagawa, JP;

Noboru Shibata, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/3459 (2013.01); H03M 13/2906 (2013.01);
Abstract

A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.


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