The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Jan. 31, 2018
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Joong Sik Kim, Yongin-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); G11C 14/00 (2006.01); H01L 29/51 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 27/1159 (2017.01); H01L 29/423 (2006.01); H01L 45/00 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 14/0027 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); H01L 21/28291 (2013.01); H01L 27/1159 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/1083 (2013.01); H01L 29/408 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/518 (2013.01); H01L 45/14 (2013.01);
Abstract

The ferroelectric memory device includes a substrate having a base doped region doped with a dopant of a first conductivity type and a trench disposed in the base doped region having an inner wall with a bottom and sidewalls. Also, the ferroelectric memory device includes a ferroelectric gate insulation layer, disposed along the inner wall of the trench, a gate electrode layer disposed on the ferroelectric gate insulation layer inside the trench, and a source region and a drain region, disposed in the substrate at respective ends of the trench and doped with a dopant of a second conductivity type. The ferroelectric memory device also includes a conductive well region, doped with a dopant of the second conductivity type. The conductive well region is disposed in the base doped region and spaced apart from the ferroelectric gate insulation layer.


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