The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Jun. 21, 2017
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Mark Himelstein, Emerald Hills, CA (US);

Kevin Rowett, Cupertino, CA (US);

Bruce Wilford, Los Altos, CA (US);

Richard Van Gaasbeck, Mountain View, CA (US);

Todd Wilde, Mountain View, CA (US);

Rick Carlson, Pacific Palisades, CA (US);

Vikram Venkataraghavan, Saratoga, CA (US);

Vishwas Durai, Los Altos, CA (US);

Blair Barnett, Mountain View, CA (US);

Assignee:

EMC IP Holding Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0831 (2016.01); G06F 12/0842 (2016.01); G06F 12/084 (2016.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0833 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 13/38 (2013.01);
Abstract

According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.


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