The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Jan. 17, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Petteri Matti Litmanen, Richardson, TX (US);

Nikolaus Klemmer, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 27/00 (2006.01); H03H 17/08 (2006.01); H03H 11/20 (2006.01); H03B 19/14 (2006.01); H03B 27/00 (2006.01); H04B 1/30 (2006.01); H03L 7/099 (2006.01); H03B 5/24 (2006.01); H03M 1/66 (2006.01); H03K 5/156 (2006.01);
U.S. Cl.
CPC ...
H04L 27/0014 (2013.01); H03B 5/24 (2013.01); H03B 19/14 (2013.01); H03B 27/00 (2013.01); H03H 11/20 (2013.01); H03H 17/08 (2013.01); H03K 5/1565 (2013.01); H03L 7/099 (2013.01); H03B 2201/0208 (2013.01); H03M 1/661 (2013.01); H04B 1/30 (2013.01);
Abstract

An oscillator architecture with pulse-edge tuning to control the pulse rising and falling edges (such as for duty cycle correction), including a signal generator with a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Pulse-edge tuning circuitry includes a high-side tuning PMOS transistor between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs to provide tuning control signals to the tuning FETs. In an example application, the oscillator design is adapted for a direct conversion RF signal chain (TX and/or RX) including an I-Path and a Q-Path: the signal generator generates ±I and ±Q differential signal frequencies.


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