The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Mar. 25, 2019
Applicant:

Txc Corporation, Taipei, TW;

Inventors:

Chien-Wei Chiang, Ping Cheng, TW;

Wan-Lin Hsieh, Ping Cheng, TW;

Chia-Wei Chen, Ping Cheng, TW;

Che-Lung Hsu, Ping Cheng, TW;

Sheng-Hsiang Kao, Ping Cheng, TW;

Chen-Ya Weng, Ping Cheng, TW;

Chia-Chen Chen, Ping Cheng, TW;

Assignee:

TXC Corporation, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 1/02 (2006.01); H03L 1/04 (2006.01); G01K 13/00 (2006.01); H01L 23/34 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
H03L 1/028 (2013.01); G01K 13/00 (2013.01); H01L 23/345 (2013.01); H03L 1/02 (2013.01); H03L 1/04 (2013.01); H05K 1/0212 (2013.01); H05K 1/181 (2013.01); H05K 1/0298 (2013.01); H05K 1/0306 (2013.01); H05K 1/184 (2013.01); H05K 2201/10075 (2013.01); H05K 2201/10151 (2013.01);
Abstract

An oven controlled crystal oscillator consisting of heater-embedded ceramic package includes a substrate, a crystal package, a crystal blank, a metal lid, a first IC chip, and a cover lid. The crystal package is mounted on the substrate, and a central bottom of the crystal package is provided with the first IC chip. The crystal blank is mounted in the crystal package and sealed by the metal lid. The crystal package has an embedded heater layer establishing a symmetric thermal field with respect to the first IC chip and the crystal blank. Alternatively, a heater-embedded ceramic carrier substrate is arranged between the first IC chip and the crystal blank to establish a symmetric thermal field with respect to the first IC chip and the crystal blank. The cover lid is combined with the substrate to cover the crystal package and the metal lid.


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