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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10510833 B1

PDFFull Text
Date of Patent:
Dec. 17, 2019

Filed:

Aug. 28, 2018

Method for manufacturing semiconductor device

Applicant:

Toyoda Gosei Co., Ltd., Kiyosu-shi, JP;

Inventors:

Takaki Niwa, Kiyosu, JP;

Takahiro Fujii, Kiyosu, JP;

Masayoshi Kosaki, Kiyosu, JP;

Assignee:

TOYODA GOSEI CO., LTD., Kiyosu-Shi, Aichi-Ken, JP;

Attorney:

McGinn I.P. Law Group, PLLC.

Primary Examiner:

Savitri Mulpuri

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/285 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02579 (2013.01); H01L 21/02584 (2013.01); H01L 21/266 (2013.01); H01L 21/26546 (2013.01); H01L 21/28264 (2013.01); H01L 21/28575 (2013.01); H01L 21/308 (2013.01); H01L 21/30621 (2013.01); H01L 29/2003 (2013.01); H01L 29/66515 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01);
Abstract

A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove.

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