The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

May. 04, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chongqing Boe Optoelectronics Technology Co., Ltd., Chongqing, CN;

Inventors:

Keke Gu, Beijing, CN;

Ni Yang, Beijing, CN;

Wei Hu, Beijing, CN;

Shaoru Li, Beijing, CN;

Xin Liu, Beijing, CN;

Zhijian Qi, Beijing, CN;

Yusong Hou, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); H01L 21/77 (2017.01); H01L 29/417 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); G02F 1/136286 (2013.01); H01L 21/77 (2013.01); H01L 27/124 (2013.01); H01L 27/1244 (2013.01); H01L 27/1248 (2013.01); H01L 29/41733 (2013.01); G02F 1/1368 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); H01L 2021/775 (2013.01);
Abstract

A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.


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