The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Aug. 13, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kazuharu Yamabe, Yokkaichi, JP;

Tatsuo Izumi, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/14 (2006.01); G11C 8/14 (2006.01); G11C 7/18 (2006.01); H01L 27/1157 (2017.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a first memory unit including first and second memory cells; a second memory unit including third and fourth memory cells; a third memory unit including fifth and sixth memory cells; a first word line coupled to gates of the first, third, and fifth memory cells; and a second word line coupled to gates of the second, fourth, and sixth memory cells. In a write operation, the first memory cell, the third memory cell, the fifth memory cell, the sixth memory cell, the fourth memory cell, and the second memory cell are written in this order.


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