The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Aug. 07, 2018
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Vinh Diep, San Jose, CA (US);

Ching-Huang Lu, Fremont, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/28 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/34 (2013.01);
Abstract

Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In a first program pass of a multi-pass program operation, pass voltages of the word lines adjacent to a selected word line are adjusted to increase electron injection in a portion of a charge-trapping layer between the selected word line and an adjacent source side unselected word line. In a second, final program pass of the multi-pass program operation, the pass voltages are adjusted to reduce electron injection in the portion of the charge-trapping layer between the selected word line and the adjacent source side unselected word line.


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