The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2019
Filed:
Jul. 24, 2017
Boe Technology Group Co., Ltd., Beijing, CN;
Beijing Boe Display Technology Co., Ltd., Beijing, CN;
Xiaoxiang Zhang, Beijing, CN;
Xi Chen, Beijing, CN;
Mingxuan Liu, Beijing, CN;
Huibin Guo, Beijing, CN;
Liping Luo, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing, CN;
Abstract
The present disclosure provides a shift register unit, a gate scanning circuit, a driving method, and a display apparatus. The shift register unit comprises a reset circuit configured to transmit a signal from a signal control terminal to a first node and a shift register unit signal output terminal under the control of a reset control signal input terminal; a first pull-down control circuit configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of a second node; and a second pull-down control circuit configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of a third node control signal input terminal coupled to a third node, so as to cooperate with the reset circuit and the first pull-down control circuit to jointly reset the shift register unit in a phase in which output of the shift register unit should not occur, thereby effectively preventing output of the shift register unit from occurring in the phase in which output of the shift register unit should not occur.