The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

May. 30, 2018
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Michitaka Hashimoto, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 17/5027 (2013.01); G06F 17/5054 (2013.01); G06F 17/5059 (2013.01); G06F 17/5072 (2013.01);
Abstract

An optimum stage number calculation method executed by a processor, the optimum stage number calculation method includes extracting information on a signal path between a transmission cell and a reception cell that transmits and receives a signal according to a clock from net information indicating a connection relationship between a plurality of cells arranged and wired in a field programmable gate array, estimating a cell total delay amount indicating a total delay amount of cells allowed to be included in one period of the clock in the signal path from input information including at least clock period information indicating a length of one period of the clock, calculating the number of stages of logic cells included in the signal path from the cell total delay amount, and outputting number-of-stages information indicating the calculated number of stages of the logic cells.


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