The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Apr. 10, 2018
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Nippon Raval, Mississauga, CA;

David A. Kaplan, Austin, TX (US);

Philip Ng, Toronto, CA;

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/14 (2006.01); G06F 12/1027 (2016.01); G06F 12/1009 (2016.01); G06F 9/455 (2018.01); G06F 12/1081 (2016.01); G06F 12/109 (2016.01); G06F 12/1018 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1475 (2013.01); G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 12/109 (2013.01); G06F 12/1027 (2013.01); G06F 12/1081 (2013.01); G06F 12/1408 (2013.01); G06F 12/1491 (2013.01); G06F 12/1018 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/151 (2013.01); G06F 2212/651 (2013.01); G06F 2212/683 (2013.01);
Abstract

An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.


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