The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Dec. 04, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Kwan-Dong Kim, Chungcheongbuk-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0611 (2013.01); G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0683 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G11C 5/04 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/222 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controller; a command delay circuit suitable for generating an effective command by delaying the command by a delay amount of the buffer control signal generation circuit in a read operation and a write operation; a data processing circuit suitable for processing write data transferred from the data buffers and transferring processed write data to the memory devices, and processing read data transferred from the memory devices and transferring processed read data to the data buffers, in response to the effective command; and a command buffer circuit suitable for transferring the effective command to the memory devices.


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