The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10505599 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 10, 2019

Filed:

Jan. 31, 2019
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Chao Shan, Milpitas, CA (US);

Mao Yu, San Jose, CA (US);

Yong Ma, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 7/0456 (2017.01); H04L 25/02 (2006.01); H04W 84/12 (2009.01);
U.S. Cl.
CPC ...
H04B 7/0456 (2013.01); H04L 25/0244 (2013.01); H04W 84/12 (2013.01);
Abstract

A plurality of circuit units of a matrix processor of a communication device are used to decompose a plurality of channel matrices, corresponding to a plurality of orthogonal frequency division multiplexing (OFDM) tones, over a plurality of cycles to determine matrix equalizer coefficients. Decomposing the plurality of channel matrices includes determining respective modes of operation for respective ones of the circuit units for respective ones of the cycles. The respective modes of operation are selected from a set of modes that includes at least one of a bypass mode for propagating input signals to output signals without altering the input signals and an idle mode for saving power when a particular circuit unit is not needed during a particular cycle. The respective circuit units are individually controlled to operate in the determined respective modes during the corresponding cycles. The determined matrix coefficients are then applied to received data signals.


Find Patent Forward Citations

Shan, Chao. (2019). Matrix equalization computation with pipelined architecture (U.S. Patent No. 10505599). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10505599

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