The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2019
Filed:
Nov. 14, 2018
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Stefan Block, Munich, DE;
Jürgen Dirks, Holzkichen, DE;
Herbert Johannes Preuthen, Dorfen, DE;
Ulrich Hensel, Radeberg, DE;
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0948 (2006.01); H01L 23/528 (2006.01); H01L 27/12 (2006.01); H01L 29/10 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 21/84 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0948 (2013.01); H01L 23/5286 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/1095 (2013.01); H01L 29/42356 (2013.01); H01L 21/84 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01);
Abstract
Structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits. A plurality of logic cells with a first well and a second well. The first well is directly connected with ground. A tap cell includes an inverter having an output connected with the second well. The inverter is configured to provide a bias voltage having a first state in which a positive voltage is supplied to the second well and a second state in which the second well is connected with ground.