The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jul. 20, 2018
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventor:

Isao Makabe, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 21/56 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66462 (2013.01); H01L 21/568 (2013.01); H01L 29/7781 (2013.01); H01L 29/7787 (2013.01); H01L 29/045 (2013.01); H01L 29/2003 (2013.01); H01L 29/41766 (2013.01); H01L 29/518 (2013.01);
Abstract

A process of forming a high electron mobility transistor (HEMT) with a reverse arrangement for the barrier layer and the channel layer thereof is disclosed. The process includes steps of epitaxially growing an oxide layer containing zinc (Zn) on a substrate where the oxide layer shows an O-polar surface; epitaxially growing a semiconductor stack made of nitride semiconductor materials on the oxide layer where the semiconductor stack includes a nitride semiconductor layer, a barrier layer and a channel layer on the oxide layer in this order; attaching a temporal substrate to the semiconductor stack; removing the substrate and the oxide layer from the semiconductor stack; attaching a support substrate to the nitride semiconductor layer; and removing the temporal substrate from the semiconductor stack.


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