The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jul. 24, 2018
Applicant:

Invensense, Inc., San Jose, CA (US);

Inventors:

Bongsang Kim, Mountain View, CA (US);

Jongwoo Shin, Pleasanton, CA (US);

Joseph Seeger, Menlo Park, CA (US);

Logeeswaran Veerayah Jayaraman, Milpitas, CA (US);

Houri Johari-Galle, San Jose, CA (US);

Assignee:

InvenSense, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01P 15/135 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 29/49 (2006.01); H01L 23/532 (2006.01); G01P 15/097 (2006.01); G01C 19/5712 (2012.01); G01C 19/5755 (2012.01); G01C 19/5762 (2012.01); G01C 19/5719 (2012.01); G01P 15/13 (2006.01); G01P 15/08 (2006.01); G01P 15/125 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4933 (2013.01); B81B 7/00 (2013.01); B81B 7/0019 (2013.01); B81B 7/0032 (2013.01); B81B 7/0035 (2013.01); B81B 7/0038 (2013.01); B81B 7/0041 (2013.01); B81C 1/00 (2013.01); B81C 1/0015 (2013.01); B81C 1/0019 (2013.01); B81C 1/00134 (2013.01); B81C 1/00158 (2013.01); B81C 1/00166 (2013.01); B81C 1/00182 (2013.01); B81C 1/00238 (2013.01); B81C 1/00261 (2013.01); G01C 19/5712 (2013.01); G01C 19/5719 (2013.01); G01C 19/5755 (2013.01); G01C 19/5762 (2013.01); G01P 15/0802 (2013.01); G01P 15/097 (2013.01); G01P 15/125 (2013.01); G01P 15/13 (2013.01); G01P 15/135 (2013.01); H01L 23/53271 (2013.01); H01L 29/4983 (2013.01); G01P 2015/0808 (2013.01);
Abstract

A method includes depositing a silicon layer over a first oxide layer that overlays a first silicon substrate. The method further includes depositing a second oxide layer over the silicon layer to form a composite substrate. The composite substrate is bonded to a second silicon substrate to form a micro-electro-mechanical system (MEMS) substrate. Holes within the second silicon substrate are formed by reaching the second oxide layer of the composite substrate. The method further includes removing a portion of the second oxide layer through the holes to release MEMS features. The MEMS substrate may be bonded to a CMOS substrate.


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